The present invention relates to semiconductor technology, and more particularly to nonvolatile memories.
FIGS. 1-8 illustrate fabrication of a conventional nonvolatile stacked-gate flash memory described in U.S. Pat. No. 6,013,551 issued Jan. 11, 2000 to J. Chen et al. Silicon oxide layer 108 (xe2x80x9ctunnel oxidexe2x80x9d) is grown on P-doped silicon substrate 150. Doped polysilicon 124 is deposited over oxide 108. Polysilicon 124 will provide floating gates for memory cell transistors.
Mask 106 is formed over the structure. Polysilicon 124, oxide 108, and substrate 150 are etched through the mask openings. Trenches 910 are formed in the substrate as a result (FIG. 2).
As shown in FIG. 3, the structure is covered with dielectric which fills the trenches. More particularly, silicon oxide 90 is grown by thermal oxidation. Then silicon oxide 94 is deposited by PECVD (plasma enhanced chemical vapor deposition). Then thick silicon oxide layer 96 is deposited by SACVD (subatomspheric chemical vapor deposition).
The structure is subjected to chemical mechanical polishing (CMP). Polysilicon 124 becomes exposed during this step, as shown in FIG. 4.
As shown in FIG. 5, ONO (silicon oxide, silicon nitride, silicon oxide) layer 98 is formed on the structure. Silicon 99 is deposited on top. Then tungsten silicide 100 is deposited.
Then a mask is formed (not shown), and the layers 100, 99, 98, 124 are patterned (FIG. 6). Layer 124 provides floating gates, and layers 99, 100 provide control gates and wordlines.
Then mask 101 is formed over the structure, as shown in FIG. 8. Silicon oxide etch removes those portions of oxide layers 90, 94, 96 which are exposed by mask 101. After the etch, the mask remains in place, as dopant is implanted to form source lines 103.
Other implantation steps are performed to properly dope the source and drain regions.
Alternative memory structures and fabrication methods are desirable.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:
(a) forming, over a semiconductor region S1, a first layer, wherein the integrated circuit is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;
(b) forming trenches in the region S1 through openings in the first layer, and filling the trenches with insulation;
(c) forming a second layer over the region S1, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell""s floating gate;
(d) patterning the second layer to form strips extending in a predetermined direction, each strip crossing over a plurality of trenches;
(e) removing that portion of the first layer over the region S1 which is not covered by the second layer, to form a plurality of first structures each of which comprises a strip made from the second layer and also comprises a portion of the first layer under the strip, each first structure having a first sidewall;
(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form a spacer over at least a portion of the first sidewall of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;
(g) removing a portion of the third layer from over a portion of the region S1 so as not to completely remove said spacers, wherein each of said cells comprises a conductive gate comprising a portion of a spacer over a first sidewall of a first structure; and
(h) introducing dopant into at least a portion of the region S1;
wherein the operations (g) and (h) are performed using a single photolithographic masking operation performed before the operation (g).
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising a nonvolatile memory, the method comprising:
(a) forming insulation on a semiconductor region S1;
(b) forming, over the insulation, a plurality of conductive first strips of first material from which floating gates are to be formed, the first strips extending in a first direction;
(c) forming trenches in the semiconductor region S1, each trench extending between adjacent first strips of the first material, the trenches containing an insulator;
(d) forming insulation over the first strips;
(e) forming second material from which conductive memory gates are to be formed, wherein the second material is formed over the insulation formed over the first material;
(f) forming a mask over the second material, and patterning the second material using said mask, to form second strips of the second material, the second strips extending in a second direction at an angle to the first strips;
(g) removing that portion of the first material over the region S1 which is not covered by the second material, to form a plurality of first structures each of which comprises a second strip of the second material and also comprises floating gates formed from the first material under the second material, each first structure having a first sidewall;
(h) forming insulation over exposed sidewalls of the floating gates and of the second material in the first structures;
(i) forming a third material over the first and second materials, and removing a portion of the third material by a process comprising an anisotropic etch, to form spacers over at least portions of the first sidewalls of each first structure;
(j) forming a mask using photolithography, the mask covering the spacers over the first sidewalls of the first structures;
(j) removing the third layer by a process comprising an etch selective to said mask, so as not to remove the spacers which are to provide conductive gates for the nonvolatile memory; and
(k) introducing dopant into the region S1, wherein the dopant is blocked by said mask from portions of the region S1.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:
(a) forming over a semiconductor region S1, a first layer comprising a plurality of first strips extending in a first direction, wherein the memory is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;
(b) forming trenches in the semiconductor region S1, each trench extending in the first direction between adjacent first strips, the trenches containing an insulation;
(c) forming, over the first layer, a second layer, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell""s floating gate, the second layer comprising a plurality of second strips extending at an angle to the first strips;
(d) removing that portion of the first layer over the region S1 which is not covered by the second layer, to form a plurality of first structures each of which comprises a second strip and also comprises a portion of the first layer under the second strip, each first structure having a first sidewall;
(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form spacers over at least portions of the first sidewalls of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;
(g) removing the third layer so as not to remove the spacers, the spacers over the first sidewalls being to provide conductive gates for the nonvolatile memory cells;
(h) introducing dopant into at least a portion of the region S1;
(i) after the operation (h), removing at least a portion of the insulation from the trenches; and
(j) after the operation (i), introducing dopant into at least a portion of the region S1 to dope at least portions of surfaces of the trenches.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit, the method comprising:
forming a first gate insulation on a semiconductor substrate for a first MOS transistor which is to be formed in a first area of the integrated circuit;
forming, over the first insulation, a layer L1 to provide a conductive gate for the first MOS transistor;
removing the layer L1 and the first insulation from a second area of the integrated circuit;
forming a second gate insulation on the semiconductor substrate in the second area for a second MOS transistor;
forming, over the second insulation, a layer L2 to provide a conductive gate for the second MOS transistor.
Some embodiments of the present invention provide a method for fabricating an integrated circuit comprising nonvolatile memory, the method comprising:
forming an insulation I1 to provide gate insulation for nonvolatile memory cells;
forming a first layer to provide floating gates for the memory cells;
removing the first layer and the insulation I1 from first, second and third areas of the integrated circuit, wherein at least one peripheral MOS transistor is to be formed in each of the first, second and third areas;
forming a first gate insulation in the first, second and third areas;
removing the first gate insulation from the second and third areas;
forming a second gate insulation in the second and third areas;
forming a second layer over the first layer, over the first gate insulation, and over the second gate insulation, wherein the memory cells and the MOS transistors in the first and third areas each have a conductive gate comprising a portion of the second layer;
removing the second layer from the second area;
forming a third gate insulation in the second area and in an area of the memory cells; and
forming a third layer, wherein the memory cells and the MOS transistor in the second area each comprises a conductive gate comprising a portion of the third layer,
wherein the first gate insulation in the first area is thicker than the second gate insulation and is thicker than the third gate insulation, and the third gate insulation is thicker than the second gate insulation.
Some embodiments of the present invention provide an integrated circuit comprising:
at least one nonvolatile memory cell having a floating gate insulated from a semiconductor substrate, and having a control gate overlying the floating gate, and having another conductive gate;
a first peripheral transistor, a second peripheral transistor, and a third peripheral transistor;
wherein a gate insulation of the first peripheral transistor is thicker than a gate insulation of the second peripheral transistor which is thicker than a gate insulation of a third peripheral transistor.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory comprising a plurality of peripheral transistors, the method comprising:
forming a first layer over first, second and third areas of the integrated circuit, wherein the memory is to include at least one memory cell formed in the first area, at least one peripheral transistor in the second area, and at least one peripheral transistor in the third area, wherein the memory cell is to include a floating gate comprising a portion of the first layer;
removing the first layer from the second and third areas;
forming a second layer in the first, second and third areas, wherein the memory cell is to include a conductive gate comprising a portion of the second layer, and the peripheral transistor in the second area is to include a conductive gate comprising a portion of the second layer;
removing the second layer from the third area;
forming a third layer over the first and third areas, wherein the memory cell is to include a conductive gate comprising at least a portion of the third layer, and the peripheral transistor in the third area is to include a conductive gate comprising at least a portion of the third layer.
Some embodiments of the present invention provide an integrated circuit comprising:
at least one nonvolatile memory cell having a floating gate insulated from a semiconductor substrate, and having a control gate overlying the floating gate, and having a conductive gate G1; and
a first peripheral transistor;
wherein the control gate is formed from a layer L1 and wherein the gate G1 and a gate of the first peripheral transistor are formed from a different layer L2.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising a nonvolatile memory array and a peripheral transistor used to operate the memory array, the method comprising:
forming, over a semiconductor substrate, a first layer to provide floating gates for the memory array;
forming, over the semiconductor substrate, a second layer overlying the first layer but insulated from the first layer, to provide conductive memory gates for the memory array;
so that the first and second layers are present over a region S1 of the semiconductor substrate, the region S1 being where the memory array is to be formed, but the first and second layers are not present over a region S2 of the semiconductor substrate, the region S2 being where a peripheral transistor for a peripheral circuitry is to be formed;
after forming the first and second layers, forming a third layer over the semiconductor substrate to provide conductive gates for the memory array, wherein each nonvolatile memory cell of the memory array has a conductive gate formed from the second layer and has a conductive gate formed from the third layer;
wherein a portion of the third layer is present over the region S2 to provide at least a portion of a conductive gate of the peripheral transistor.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:
forming, over a semiconductor substrate, a first layer to provide floating gates for the memory array;
forming, over the semiconductor substrate, a second layer overlying the first layer but insulated from the first layer, wherein the memory is to have a plurality of conductive gates each of which comprises a portion of the second layer;
patterning the second layer to provide at least one structure comprising a strip of the second layer and also comprising floating gates under the strip of the second layer, the floating gates being formed from the first layer, wherein the memory is to have a plurality of cells each of which comprises a conductive gate comprising a portion of the strip of the second layer, wherein the structure has a sidewall;
depositing a third layer over said structure, wherein each of said cells is to have a conductive gate comprising a portion of the third layer and formed over the sidewall of said structure;
forming a mask over the third layer, and etching the third layer anisotropically to provide a spacer line over the sidewall of said structure in a region not covered by the mask, wherein each of said cells is to have a conductive gate comprising a portion of said spacer line, wherein a third layer portion covered by the mask comprises extensions to the spacer line;
forming an insulator over the first, second and third layers, and forming a conductive layer contacting the extension through openings in the insulator.
Some embodiments of the present invention provide an integrated circuit comprising nonvolatile memory comprising:
a structure comprising a conductive line L1 providing first conductive gates for a plurality of memory cells, the structure also comprising a plurality of floating gates formed under the conductive line L1 and insulated from the conductive line L1;
a conductive line L2 formed as a spacer on a sidewall of said structure and providing second conductive gates for said memory cells, each of said memory cells comprising one of said first conductive gates and one of said second conductive gates;
wherein said structure, said floating gates, and said conductive lines L1 and L2 are formed over a semiconductor substrate;
wherein the substrate comprises:
a plurality of trenches formed therein and extending at an angle to said structure; and
a conductive area extending along said structure traversing a plurality of said trenches, the conductive area providing source/drain regions for said memory cells.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:
(a) forming over a semiconductor region S1, a plurality of first strips of a first material from which floating gates are to be formed, the first strips extending in a first direction;
(b) forming over the semiconductor region S1, a plurality of second strips of a second material, the second strips extending in a second direction at an angle to the first direction, thereby creating regions bounded by the first and second strips;
(c) forming trenches in the region S1 in the areas bounded by the first and second strips, and filling the trenches with insulation;
(d) forming a material L1 from which conductive memory gates are to be formed, wherein the material L1 is formed over the first material, and is insulated from the first material;
(e) forming a mask over the material L1, and patterning the material L1 using said mask, so that the material L1 is removed from over at least a portion of each of the first strips;
(f) removing the first material not covered by the material L1 over the region S1, to form a plurality of first structures each of which includes the first material and the material L1 overlying the first material;
(g) insulating at least one sidewall of each first structure;
(h) forming a third material over the first material and the material L1;
(i) etching the third material by a process comprising an anisotropic etch, to form a spacer on at least one sidewall of each of the first structures; and
(j) doping at least portions of those areas of the region S1 over which the first material has been removed and of those areas of the region S1 over which the second strips were formed;
wherein the nonvolatile memory comprises floating gate regions formed from the first material, conductive gate regions formed from the material L1, and conductive gate regions formed from the third material.
Some embodiments of the present invention provide a method for manufacturing an integrated circuit comprising nonvolatile memory, the method comprising:
(a) forming, over a semiconductor region S1, a first layer, wherein the integrated circuit is to include a plurality of nonvolatile memory cells each of which has a floating gate comprising a portion of the first layer;
(b) forming trenches in the region S1 through openings in the first layer, and filling the trenches with insulation;
(c) forming a second layer over the region S1, wherein each of said cells is to have a conductive gate comprising a portion of the second layer, the conductive gate being insulated from the cell""s floating gate;
(d) patterning the second layer to form strips extending in a predetermined direction, each strip crossing over a plurality of trenches;
(e) removing that portion of the first layer over the region S1 which is not covered by the second layer, to form a plurality of first structures each of which comprises a strip made from the second layer and also comprises a portion of the first layer under the strip, each first structure having a first sidewall;
(f) forming a third layer over the first and second layers, and removing a portion of the third layer by a process comprising an anisotropic etch, to form a spacer over at least a portion of the first sidewall of each first structure, each spacer being insulated from materials of the first and second layers in the respective first structure;
(g) removing a portion of the third layer from over a portion of the region S1 so as not to completely remove said spacers, wherein each of said cells comprises a conductive gate comprising a portion of a spacer over a first sidewall of a first structure; and
(h) introducing dopant into at least a portion of the region S1.
Some embodiments of the present invention provide a method for erasing memory cells of a flash memory array formed in and over a semiconductor region, the memory array comprising a plurality of sections each of which can be erased individually, each section having a plurality of memory cells, the method comprising:
receiving by the memory a command indicating whether the entire memory array is to be erased or less than the entire memory array is to be erased;
if the entire memory array is to be erased, then erasing the entire memory array;
if less than the entire memory array is to be erased, then erasing a portion of the memory array without erasing the entire memory array.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.